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VLSI RTL Design & Verification

Become an expert in digital circuit design and verification. Learn Verilog, SystemVerilog, UVM, and industry best practices from semiconductor experts.

24
Weeks Training
100%
Placement Assistance
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Course Details

Comprehensive training covering everything from basic digital design to advanced verification methodologies

Duration & Format

24 weeks intensive training • Live online classes • Hands-on labs

Skill Level

Beginner to Advanced • Basic knowledge of digital electronics recommended • Perfect for career switchers

Certification

Silicademy certificate upon completion • Industry-recognized • Portfolio of real-world projects • LinkedIn profile optimization

Course Curriculum

Structured learning path from fundamentals to advanced verification techniques

Module 1: Digital Design Fundamentals

  • Number Systems
  • Logic Circuits & Boolean Algebra
  • Combinational Circuits
  • Adders & Subtractors
  • Encoders & Decoders
  • Mux & DeMux
  • Sequential Logical Circuits
  • Latches & Flipflops
  • Registers & Counters
  • Finate State Machines
  • Glitches & Hazards

Module 2: Verilog (Hardware Description Language)

  • Verilog: History, Evolution, and Applications
  • Lexical Conventions in Verilog
  • Data Types in Verilog
  • Verilog Operators and Expressions
  • Control Flow and Procedural Blocks
  • begin-end and fork-join in Verilog
  • Tasks and Functions in Verilog
  • Verilog System Functions and Tasks
  • Parameterized Module in Verilog
  • Verilog Scheduling Regions
  • Verilog Clock Generator
  • Verilog Macros and Directives
  • Verilog Testbench

Module 3: SystemVerilog for Design & Verification

  • Introduction to SystemVerilog
  • SystemVerilog Data Types
  • SystemVerilog Arrays
  • SystemVerilog OOP
  • SystemVerilog Classes & Objects
  • SystemVerilog Encapsulation
  • SystemVerilog Inheritance
  • SystemVerilog Polymorphism
  • SystemVerilog Randomization
  • SystemVerilog Constraints
  • SystemVerilog Interprocess Communication (IPC)
  • SystemVerilog Fork-Join: Concurrent Processes
  • SystemVerilog Interfaces
  • SystemVerilog Modports
  • SystemVerilog Clocking Blocks
  • SystemVerilog Virtual Interfaces
  • SystemVerilog Coverage
  • SystemVerilog Code Coverage
  • SystemVerilog Functional Coverage
  • SystemVerilog Assertions
  • SystemVerilog Immediate Assertions
  • SystemVerilog Concurrent Assertions
  • SystemVerilog Event Regions
  • SystemVerilog Testbench

Module 4: Universal Verification Methodology (UVM)

  • Introduction to UVM
  • UVM Testbench Hierachy
  • UVM Objects
  • UVM Components
  • Reportimg Mechanism
  • Phases
  • TLM - Transaction Level modeling
  • UVM config_db
  • UVM Factory
  • UVM Driver, Monitor and Scoreboard components Code
  • Virtual Sequence & Virtual Sequencer
  • UVM Callbacks
  • UVM Events
  • RAL - Register Abstraction Layer

Module 5: Industry Protocols

  • APB (Advanced Peripheral Bus)
  • AHB (Advanced High-performance Bus)
  • AXI (Advanced eXtensible Interface)
  • SPI (Advanced eXtensible Interface)
  • DDR (Double data rate)

Module 6: Project

  • Design specification and architecture planning
  • RTL implementation of complex digital system
  • Developing comprehensive UVM testbench
  • Verification planning and coverage closure
  • Final project presentation and review
  • Industry mentorship and feedback

Tools & Technologies

Master industry-standard tools used by leading semiconductor companies

Verilog/SystemVerilog

Hardware description and verification languages

UVM Framework

Universal Verification Methodology

QuestaSim

Industry-standard simulation tools

Protocol Verification

DDR, AXI, AHB, APB, I2C, SPI, UART

Coverage Tools

Functional & Code Coverage Analysis

Debug Tools

Waveform Debugging

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